Field of the Invention
The present invention relates to an information processing apparatus that uses an SRAM having a low power consumption mode, and a method for controlling the same.
Description of the Related Art
Recently, microfabrication of semiconductor integrated circuits has increasingly advanced, which has made it possible to integrate a logic circuit and an SRAM, which had been separated into a plurality of chips, into a single chip. However, more leakage current tends to flow through the devices with the increasing reduction in the size thereof. Shutdown of the power supply through power supply separation within a chip is available as a technique to reduce power consumption due to leakage current, but data held in a semiconductor memory, such as an SRAM, is lost due to the shutdown of the power supply, and accordingly, the held data needs to be temporarily saved at the time of the shutdown of the power supply. In this case, the data needs to be copied from a memory area in which the data was temporarily saved at the time of restoration from the shutdown of the power supply, and the restoration takes time.
To solve the above problem, Japanese Patent Laid-Open No. 2012-094228 proposes a technique to reduce leakage current in a state of holding data in an SRAM to save power consumption. This technique enables data to be held while saving power by applying a minimum voltage to a memory array unit to allow stored data to be held and interrupting a power supply to circuits that are not necessary to hold the stored data, such as peripheral circuits. In the following description, a state of thus holding the stored data in a memory module with a minimum current will be referred to as a resume-standby mode (RS mode), and states other than the RS mode will be referred to as a normal mode. When the stored data does not need to be held in the memory array unit, a further power-saving state can be achieved by also interrupting a power supply to the memory array unit. Such a state where the power supply to the memory module is interrupted will be referred to as a power supply cutoff mode.
Incidentally, chips mounted in a digital multifunctional machine are provided with various image processing circuits for scanning, printing, and the like. In these image processing circuits, SRAMs are commonly used for storing tables for various image processing coefficients, and also used as line buffers to hold an intermediate image. Japanese Patent Laid-Open No. 2014-201034 describes controlling of dither processing in image formation processing so that use positions of light emitting elements and print elements are not fixed to prevent deterioration over time. In addition, the recent advances of semiconductor technology have made it possible to integrate a plurality of chips, increasing the capacity of SRAMs within the chips. The proportion of the power consumption in the SRAMs to the entire power consumption in a chip that is in operation tends to increase accordingly. For this reason, there is a need for a reduction in the power consumption in the SRAMs to the greatest extent possible, using an SRAM power saving technique, such as an SRAM having the RS mode (which will be referred to as a resume-SRAM).
However, the aforementioned conventional technique has the following problems. For example, regarding the aforementioned conventional technique, only power saving control for an entire SRAM area has been considered. However, in many cases, various kinds of image processing such as scanning and printing are performed on a certain pixel (which will be called a pixel of interest), using image data in a predetermined area with the pixel of interest at the center (e.g. 5×5 pixels including the pixel of interest, two pixels above and below the pixel of interest, and two pixels on the left and right sides of the pixel of interest). In this case, image processing is executed on the pixel of interest by reading out only the image data in the area necessary for image processing (pixel data within the 5×5 window) from the SRAM. That is to say, if power saving control can be performed corresponding to the pixel level in the image processing, power consumption in the SRAM can be considerably reduced.
In other words, at any timing while image processing is executed, power does not need to be supplied in the normal mode to SRAM areas that hold image data other than target image data and any other data. Accordingly, it is desirable to perform control so as to activate, in the normal mode, the SRAM area in which the target pixel data is held only when accessing this area, and hold data in the other SRAM areas in the RS mode.